1. Field of the Invention
This invention relates to a control method of a semiconductor memory device having a plurality of operation modes and a semiconductor memory device, and particularly to a control method of a semiconductor memory device which enables performing suitable individual operation controls when the respective operations modes are independently executed, and a semiconductor memory device.
2. Description of Related Art
FIG. 20 is a circuit block diagram showing a semiconductor memory having a memory cell array divided into a plurality of banks B0 to BN. Here, a non-volatile semiconductor memory such as a flash memory is described as an exemplary semiconductor memory.
In the non-volatile semiconductor memory having the multi-bank structure shown in FIG. 20, write switch circuits 1010 to 101N and read switch circuits 1040 to 104N are provided for the banks B0 to BN, respectively. Each of the switch circuits is independently selected corresponding to the banks B0 to BN, thus enabling setting of an operation mode for each bank. The operation modes include a data readout (hereinafter simply referred to as READ) operation mode and a data write (hereinafter simply referred to as WRITE) operation mode, and the WRITE mode included a program (hereinafter simply referred to as PGM) operation mode and a data erase (hereinafter simply referred to as ER) operation mode, as will be later described with reference to FIGS. 21A to 21C.
When the WRITE mode is set, one of the write switch circuits (one of 1010 to 101N) is selected and therefore a necessary bias voltage VX corresponding to the PGM/ER mode is supplied to a selected bank (one of B0 to BN) via the write switch circuit. The bias voltage VX is generated at a voltage generator circuit 106. The voltage to be generated is a voltage between a normal bias voltage from a ground voltage VSS to a power source voltage VCC used in the data readout operation such as the READ operation and a high bias voltage such as a negative voltage lower than the ground voltage VSS or a positive voltage higher than the power source voltage VCC. In accordance with an enable signal EX of a predetermined bias voltage VX outputted from a write control circuit 105, the voltage generator circuit 106 starts the operation to generate the bias voltage VX. Enable signals EnX (E0X to ENX) similarly outputted from the write control circuit 105 are inputted to the write switch circuits 1010 to 101N, respectively, to control opening and closing of the write switch circuits 1010 to 101N.
When the READ mode is set, one of the read switch circuits (one of 1040 to 104N) is selected and therefore a data current is read out from a selected bank (one of B0 to BN) via the read switch circuit. The read-out data current is differentially amplified at a sense amplifier 108 with a reference current outputted from a reference cell 109. The differential amplification is carried out after the current is converted to a voltage value, if necessary. The sense amplifier 108 is controlled by a read control signal RDC outputted from a read control circuit 107.
In FIG. 20, the write control circuit 105, the voltage generator circuit 106, the read control circuit 107 and the sense amplifier 108 are provided as one set in the semiconductor memory. On the other hand, the write switch circuits 1010 to 101N and the read switch circuits 1040 to 104N for selecting banks as objects of operation are provided for the respective banks. This enables the READ mode and the WRITE mode to operate at independent timing for different banks.
As described above, the READ operation and the WRITE operation separately operate at independent timing for the respective banks. Moreover, the respective operations themselves are intrinsic, as shown in FIGS. 21A to 21C.
As shown in FIG. 21A, in the READ operation, a readout operation is carried out by reading data stored in the memory cell as a data current and differentially amplifying the data current with a reference current. Specifically, when transition of address ADD is detected by the read control circuit 107 (FIG. 20), a high pulse is outputted as an address transition detector signal ATD. At the same time, a data path via the read switch circuit and a reference current path from the reference cell 109 are set up and a data current Idata and a reference current Iref start to flow. Following the high pulse of the address transition detector signal ATD, an equalize signal EQ shifts to a high level to initialize the sense amplifier 108. During this time, the data current Idata and the reference current Iref shift to a predetermined current level. At a point when the predetermined current level is reached, the equalize signal EQ shifts to a low level while a sense amplifier activation signal LT becomes a high pulse. During this high-pulse period, the sense amplifier 108 performs the differential amplification operation. Generally, the differential amplification operation is carried out after the data current Idata and the reference current Iref are converted to voltages. The above-described READ operation enables reduction in access time by the proper arrangement in the circuit structure and thus enables operation with an access time of nanoseconds (nsec).
On the other hand, the WRITE operation such as the PGM operation shown in FIG. 21B and the ER operation shown in FIG. 21C is carried out by a change in physical status, that is, the presence/absence of electrons at a floating gate of the memory cell. Physical phenomena of passage of electrons through a gate oxide film are necessary such as injection of electrons using hot electrons and emission of electrons using FN tunneling. To generate such physical phenomena decided by physical elements such as process technology and device structure, a high electric field due to application of a high voltage difference is necessary.
Specifically, during a PGM period following a program verification (hereinafter simply referred to as PGMV) period, positive voltages are applied to a word line WL, which is a control gate terminal of the memory cell, and a bit line BL, which is a drain terminal (for example, 9 V to the word line WL and 5 V to the bit line BL). During an ER period following an erase verification (hereinafter simply referred to as ERV) period, a negative voltage is applied to the word line WL and a positive voltage is applied to a well WELL, which is a back gate constituting a channel region (for example −9 V to the word line WL and 9 V to the well WELL).
As the PGM/ER period, for example, an access time of microsecond (◯sec) is necessary. While transition of threshold voltage of the memory cell is confirmed during the PGMV/ERV period, the similar operation is repeated until the threshold voltage of the memory cell reaches a predetermined threshold voltage. To complete the PGM/ER operation, for example, an access time of millisecond (msec) is necessary.
However, in the conventional semiconductor memory, in the READ operation, the data current Idata and the reference current Iref are converted to a data voltage Vdata and a reference voltage Vref, respectively, and a small amplitude voltage difference is differentially amplified in an access time of nanosecond (nsec). On the other hand, in the WRITE operation, a high bias voltage is repeatedly applied in a cycle of microsecond (◯sec) within a time of millisecond (msec) until the completion of the operation. Moreover, the READ operation and the WRITE operation separately operate at independent timing. Therefore, voltage transition between a normal bias voltage from the ground voltage VSS to the power source voltage VCC used in the READ operation and a high bias voltage such as a negative voltage lower than the ground voltage VSS or a positive voltage higher than the power source voltage VCC may be a noise source to the data voltage Vdata and the reference voltage Vref. As a result of reduction in small amplitude voltage difference to be differentially amplified at the sense amplifier 108, the data may be inverted and differentially amplified, causing a problem that false data may be outputted.
When voltage transition of the bias voltage VX from a positive voltage to a normal bias voltage or from a normal bias voltage to a negative voltage occurs, if lowering voltage transition has capacitive coupling with a data voltage Vdata of data “0”, the small amplitude voltage difference from the reference voltage Vref is reduced and the margin of differential amplification is reduced. If capacitive coupling with the reference voltage Vref occurs, the small amplitude voltage difference from a data voltage Vdata of data “1” is reduced, causing a problem that the margin of differential amplification is reduced.
When voltage transition of the bias voltage VX from a normal bias voltage to a positive voltage or from a negative voltage to a normal bias voltage occurs, if boosting voltage transition has capacitive coupling with a data voltage Vdata of data “1”, the small amplitude voltage difference from the reference voltage Vref is reduced and the margin of differential amplification is reduced. If capacitive coupling with the reference voltage Vref occurs, the small amplitude voltage difference from a data voltage Vdata of data “0” is reduced, causing a problem that the margin of differential amplification is reduced.
Moreover, the case where voltage transition of the bias voltage VX changes a substrate bias voltage by capacitive coupling with the substrate of the semiconductor memory can also be considered. The properties such as threshold voltage of each transistor arranged on the substrate change and may adversely affect the differential amplification operation of the small amplitude voltage difference. This is a problem.
In the case where the write control circuit 105, the voltage generator circuit 106, the read control circuit 107, the sense amplifier 108 and the like are provided as one set in the semiconductor memory, as shown in FIG. 20, the relation of arrangement with the banks B0 to BN varies by each bank. It can be also considered that a voltage change of the bias voltage VX may have large influence due to the relation of arrangement. In the case where a change position of the substrate bias voltage due to voltage transition and the source of the substrate bias voltage are away from each other, there is a problem that the change in the substrate bias voltage and deviation of the substrate bias voltage on the substrate may be left for a long time.